Currently, three-dimensional memory devices with different structures, such as NAND flash memories including a plurality of stacked thin film transistors, have been developed in the industry to achieve higher storage capacity. Specifically, a conventional three-dimensional memory includes a plurality of bit lines, a plurality of source lines and a plurality of vertically stacked memory layers. Each of the memory layers includes a plurality of word lines. Additionally, the conventional three-dimensional memory further includes a plurality of vertical channels passing through the memory layers, and each of the word lines and the vertical channels passing through the memory layers define a plurality of memory cells.
Generally, the conventional three-dimensional memory can be programmed and read by controlling the voltages applied to the word lines, the bit lines, and the source lines. To be more specific, a plurality of memory cells vertically arranged between the corresponding bit line and the corresponding source line are connected in series.
However, when write states of the serially connected memory cells are read, two different voltages are respectively applied to the corresponding one of the bit lines and the corresponding one of the source lines, a read voltage is sequentially applied to each of the word lines along the vertical direction from bottom to top (or from top to bottom), and then the current value corresponding to each of the word lines is measured to determine the write state of each of the memory cells. That is to say, when the conventional three-dimensional memory is read, the read sequence of the memory cells cannot be changed arbitrarily. Only if the memory cells are read in a particular sequence (from top to bottom or from bottom to top) will the write state of each of the memory cells be determined, thereby affecting the speeds of writing and reading.
Furthermore, when the conventional three-dimensional memory is programmed and read, program disturbance and read disturbance in non-selected memory cells usually come up, which affects the device window and the performance of the memory device.